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Renesas Electronics /R7FA6M3AH /EDMAC0 /TRIMD

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Interpret as TRIMD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TIS 0 (0)TIM

TIS=0, TIM=0

Description

Transmit Interrupt Setting Register

Fields

TIS

Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt.

0 (0): Transmit Interrupt is disabled.

1 (1): Transmit Interrupt is enabled.
TIM

Transmit Interrupt Mode

0 (0): Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted.

1 (1): Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data